Synopsys Design Compiler Tutorial 2021 File
# Save the synthesized design write -format ddc -hierarchy -output outputs/final.ddc write -format verilog -hierarchy -output outputs/final_netlist.v Save SDC constraints (for placement & routing) write_sdc outputs/constraints_out.sdc Step 9: Common Pitfalls in the 2021 Version 1. "Undriven port" warnings Fix: Use set_driving_cell on all input ports. DC 2021 is stricter about floating inputs. 2. "DesignWare license not found" Fix: Ensure synthetic_library is set correctly. Without this, you get "Unknown operator" errors for + , - , * . 3. Hold time violations reported after compile Note: DC 2021 does not fix hold timing. It only fixes setup. Hold fixes happen in PrimeTime or ICC2 using clock tree insertion. Ignore hold violations in DC unless they are > 0.5ns. Step 10: Full Script Example (run.tcl) Save this as run_synthesis.tcl and execute with dc_shell -f run_synthesis.tcl .
# .synopsys_dc.setup set search_path [list . /home/designs/rtl /tools/libs/SAED32_EDK/lib/stdcell] set target_library "saed32nm_tt_1p05V_25C.db" set link_library [list "*" $target_library saed32nm_io.db] set symbol_library "saed32nm.sdb" set synthetic_library "dw_foundation.sldb" set hdlin_auto_save_def true set vem_enable false # Disable Visual Environment if running scripts synopsys design compiler tutorial 2021
# ---------------------------------------- # Synopsys DC 2021 Tutorial Script # ---------------------------------------- set my_design "riscv_core" set target_library "saed32nm_tt_1p05V_25C.db" set link_library "* $target_library" set search_path ". ./rtl ./libs" Read RTL read_file -format verilog [list $my_design.v memory_controller.v] current_design $my_design link Apply Constraints create_clock -name core_clk -period 5.0 [get_ports clk] set_input_delay -clock core_clk -max 1.5 [all_inputs] -remove [get_ports clk] set_output_delay -clock core_clk -max 1.5 [all_outputs] Pre-compile checks check_design check_timing Compile compile_ultra -timing Reports report_timing > reports/$my_design.timing report_area > reports/$my_design.area Save write -format verilog -output outputs/$my_design.v write_sdc outputs/$my_design.sdc # Save the synthesized design write -format ddc
dc_shell -gui Alternatively, use the command-line mode for batch scripts: reports/$my_design.timing report_area >